1. Field of the Invention
The present invention relates to a method for fabricating structures of etch-resistant metal/semiconductor compound on a substrate through, in particular but not exclusively, X-ray or extreme ultraviolet (EUV) lithography.
2. Brief Description of the Prior Art
Due to the predicted diminution of the critical dimension in integrated circuits, deep ultraviolet lithography will be replaced as the main lithographic tool for industrial production within five years [“Potentials and challenges for lithography beyond 193 nm optics” John Canning, J. Vac. Sci. Technol. B 15(6), November/December 1997, pp. 2109-2111]. X-ray lithography and EUV lithography are potential replacement technologies which both use light to transfer patterns from a mask to a wafer on which an integrated circuit is fabricated.
In the case of X-ray lithography, one of the major areas of concern is the difficulty to produce masks with sufficient resolution and with no defects. Also, these masks will be submitted, during production, to a large amount of thermal stresses caused by the absorption of the X-rays [“Process technologies for Ta/SiC X-ray masks”, M. Yamada, K. Kondo, M. Nakaishi, J. Kudo, K, Sugishima, J. Electrochem. Soc. 137 (7), July 1990, pp. 2231-2242]. The ability to produce a mask with high resolution has already been demonstrated by electron beam lithography [“Challenges and progress in X-ray lithography” Jerome P. Silverman, J. Vac. Sci. Technol. B 16(6), November/December 1998, pp. 3137-3141]. However, the throughput of mask production is limited by the high quality criteria that each mask has to fulfill and by the limited speed of electron beam lithography. To increase the throughput of mask production, one strategy would be to copy an original mask made by electron beam lithography. X-ray lithography generally uses conventional photon-sensitive resists to transfer the patterns from the mask to a wafer, and these resists are not suitable for sub-100 nm pattern transfer to a thick layer of absorber with vertical sidewalls such as needed for mask copying. This is mainly due to the poor resistance of those resists to plasma etching. In turn, the ability of structures of silicide or other metal/semiconductor compound to adequately protect an absorbent layer during plasma etching has already been demonstrated in relation to electron beam lithography [“Method for fabricating submicron silicide structures on silicon using a resistles lectron beam lithography process” D. Drouin, J. Beauvais, R. Lemire, E. Lavallee, R. Gauvin, M. Caron, Appl. Phys. Lett. 70 (22), 2 Jun. 1997, pp. 3020-3022; and “Fabrication of sub-micron silicide structures on silicon using resistless electron beam lithography” J. Beauvais, D. Drouin, E. Lavallee, U.S. Pat. No. 5,918,143, 29 Jun. 1999].
The same kind of absorbent as for X-ray lithography masks are being considered for EUV lithography masks [“Extreme ultraviolet lithography”, C. W. Gwyn, R. Stulen, D. Sweeney, D. Attwood, J. Vac. Sci. Technol. B, 16 (6), November/December 1998, pp. 3142-3149]. The wavelengths being considered for EUV lithography are of the order of 10-20 nm, which requires for adequate absorption a thickness of approximately 100 nm of metal. This absorbent is spaced apart by a buffer layer, typically a 50 nm thick layer of SiO2 or SION. In the case of EUV, one of the critical issues is the ability to etch the absorbent and the buffer layer with vertical sidewalls and achieve identical effective widths for both layers [“Study of removal process for buffer layer on multilayer of EUVL mask”, E. Hoshino, T. Ogawa, M. Takahashi, H. Hoko, H. Yamanashi, N. Hirano, A. Chiba, B-T Lee, M. Ito, S. Okazaki, Prooceedings of the 17th European Mask Conference in Munich, 13-14 November 2000, pp. 27-317]. This requires a great level of chemical selectivity between both etches used to transfer the patterns to the absorbent and the buffer layer.
Another application of structures of silicide or other metal/semiconductor compound in microelectronics is the fabrication of transistor gates having a low electrical resistivity. Previously, the fabrication of transistor gates was limited in speed by the electron beam lithography processes used to form the silicide or other metal/semiconductor compound [“Salicidation process for submicrometre gate MOSFET fabrication using a resistless electron beam lithography process” S. Michel, E. Lavallee, J. Beauvais, J. Mouine, Electronics Letters, 35 (14), 22 Jul. 1999, pp. 1283-1284] or in resolution by the patterning of the gate [“Salicidation process using NiSi and its device application” F. Deng, R. A. Johnson, P. M. Asbeck, S. S. Lau, W. B. Dubbelday, J. Appl. Phys., 81 (12), 1997, pp. 8047-8051]. To overcome these limitations, a high resolution projection lithographic technique is required. The direct formation of silicide or other metal/semiconductor compound by X-rays or EUV meets with these requirements.